Shows the usage of basic gates like AND, OR, XOR and NOT.
Also uses switches for input and LEDs for output. Click on a switch (square with "0") to toggle.
A half adder adds two bits. The output bit "s" is the sum, "c" is the carry.
You can either build a half adder using two basic gates or you just use the half adder element.
The full adder does the same as the half adder, but can add three bits.
In case all three input connectors are set to HIGH (1) the sum and carry output would also be HIGH (1).
You can build a full adder using two half adders and an OR gate. Or just use the full adder element.
A D-Latch can (like other latches/flip-flops) hold a state. It can save a single bit.
D-Latches have one input connector for data and one clock connector. On falling edge the new value gets stored. In simulation mode you can emit clock signals using the clock controls on the left side.
You can build a simple 4-bit register using 4 d-latches. In this sample all latches are controlled by the same clock signal.Open sample
A binary counter increases its output value by one on each clock tick. In this sample 4 d-latches are used.
Only the first latch is connected to the clock, the other ones are using the output of the previous latch as clock signal.
In this sample a diode matrix is used to map from 4 different traffic light phases (red, red-yellow, green, yellow) to the proper light.
A diode only let signals pass from horizontal to vertical wires.
Adds two 4-Bit numbers. All carry bits are passed to the next full adder. The last carry bit (integer overflow) is the shown next to the output.Open sample
Like the previous sample, but serial implementation. A 2-bit counter with multiplexer selects the correct input bits. Afterward both bits gets added to the previous carry bit and the result is saved in a shifting register.Open sample
A simple 4-bit CPU with 12 instructions. You can find a manual on the board. The initial program stored in the ROM (which is a diode matrix) just counts upwards. To start the CPU generate a continuous clock signal. If the simulation is too slow, just deactivate the frame/logic tick synchronization.Open sample
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